1. Field of the Invention
The present invention relates to a low voltage driven type sense amplifier and, more particularly, to a dynamic RAM (to be referred to as a DRAM hereinafter).
2. Description of the Related Art
FIG. 1 shows the schematic layout of the memory cell array portion of a general DRAM. FIG. 2 shows a circuit example of the memory cell array portion.
A memory cell array 11 is constituted by a plurality of memory cells arranged in a matrix. A plurality of word lines WL that run in the row direction and a plurality of bit lines BL that run in the column direction are arranged on the memory cell array 11. The plurality of bit lines BL normally form bit line pairs each of which includes two bit lines BLt and BLc, as shown in FIG. 2.
Sense amplifiers S/A are connected to the pairs of bit lines BLt and BLc to read/write data from/in the memory cell array 11. In this example, each sense amplifier S/A is constituted by two inverter circuits P1, N1, P2, and N2 which are flip-flop-connected. A P channel MOS transistor P3 is connected to a power supply node PN1 of the sense amplifier S/A to supply, e.g., a potential VBLH to the power supply node PN1. An N channel MOS transistor N3 is connected to a power supply node PN2 of the sense amplifier S/A to supply, e.g., a ground potential VSS to the power supply node PN2.
The sense amplifier S/A is controlled by control signals SEP and SEN. The sense amplifier S/A is activated when the control signal SEP is “L” and the control signal SEN is “H”.
A sense amplifier equalizer SAE has a function of equalizing the potentials of the two power supply nodes PN1 and PN2 of the sense amplifier S/A. The sense amplifier equalizer SAE is constituted by N channel MOS transistors N4, N5, and N6. The N channel MOS transistor N4 has a function of short-circuiting the two power supply nodes PN1 and PN2. The N channel MOS transistors N5 and N6 have a function of supplying a precharge potential VBL to the two power supply nodes PN1 and PN2.
The sense amplifier equalizer SAE is controlled by a control signal SAEQL. When the control signal SAEQL is “H”, the sense amplifier equalizer SAE equalizes the two power supply nodes PN1 and PN2 to the precharge potential VBL.
A bit line equalizer BLE has a function of equalizing the potentials of the pair of bit lines BLt and BLc. The bit line equalizer BLE is constituted by N channel MOS transistors N7, N8, and N9. The N channel MOS transistor N7 has a function of short-circuiting the pair of bit lines BLt and BLc. The N channel MOS transistors N8 and N9 have a function of supplying the precharge potential VBL to the pair of bit lines BLt and BLc.
The bit line equalizer BLE is controlled by a control signal EQL. When the control signal EQL is “H”, the bit line equalizer BLE equalizes the pair of bit lines BLt and BLc to the precharge potential VBL.
Note that the arrangement of the memory cell array portion is described in, e.g., patent references 1 to 4.
The operation of the memory cell array portion shown in FIG. 2 in read operation will be described next with reference to the waveform chart shown in FIG. 3.
First, when the control signals EQL and SAEQL change to “H”, the pair of bit lines BLt and BLc and the power supply nodes PN1 and PN2 of the sense amplifier S/A are equalized to the precharge potential VBL.
Then, when the control signals EQL and SAEQL change to “L”, equalization of the pair of bit lines BLt and BLc and the power supply nodes PN1 and PN2 of the sense amplifier S/A is canceled. The pair of bit lines BLt and BLc and the power supply nodes PN1 and PN2 of the sense amplifier S/A are set at the precharge potential VBL and in a floating state.
When the potential of the selected word line WL rises, a potential difference corresponding to the data of the memory cell connected to the selected word line WL is generated between the pair of bit lines BLt and BLc. When a sufficient potential difference is generated between the pair of bit lines BLt and BLc, the sense amplifier S/A is activated.
More specifically, when the control signal SEP is set to “L” and the control signal SEN is set to “H”, the power supply node PN1 (SAP) changes to “H” and the power supply node PN2 (bSAN) changes to “L”, so the sense amplifier S/A is activated. As a result, the potential difference between the pair of bit lines BLt and BLc is amplified.
After that, the potential of the selected word line WL is dropped to stop the access to the memory cell. In addition, the control signal SEP is set to “H”, and the control signal SEN is set to “L” to inactivate the sense amplifier S/A. Furthermore, the control signals EQL and SAEQL are set to “H” to equalize the pair of bit lines BLt and BLc and the power supply nodes PN1 and PN2 of the sense amplifier S/A.
Patent references relating to the related art will be showed below.
Patent reference 1: Jpn. Pat. Appln. KOKAI Publication No. 5-291535
Patent reference 2: Jpn. Pat. Appln. KOKAI Publication No. 2000-215676
Patent reference 3: U.S. Pat. No. 6,181,618
Patent reference 4: U.S. Pat. No. 6,285,613
As shown in FIG. 2, both the bit line equalizer BLE and the sense amplifier equalizer SAE are constituted by only N channel MOS transistors. In this case, the equalizing operation may delay depending on the threshold voltage of the MOS transistors. To prevent this, a power supply voltage VCC that is higher than the “H”-level voltage, i.e., the potential VBLH to be applied to the pair of bit lines BLt and BLc is normally used as the “H”-level voltage of the control signals EQL and SAEQL that control the equalizers BLE and SAE.
Additionally, as shown in FIGS. 1 and 2, the bit line equalizer BLE is normally arranged adjacent to the sense amplifier S/A. One bit line equalizer BLE is arranged in correspondence with each sense amplifier S/A (each pair of bit lines BLt and BLc). However, only one sense amplifier equalizer SAE is arranged in correspondence with a plurality of sense amplifiers S/A. For this reason, the sense amplifier equalizers SAE are arranged in dedicated areas prepared every plurality of sense amplifiers S/A.
FIG. 4 shows a layout example of the sense amplifier S/A and equalizers BLE and SAE in a chip.
As described above, the power supply voltage VCC applied to the equalizers BLE and SAE is higher than the voltage VBLH applied to the sense amplifier S/A. For this reason, the gate oxide film of each MOS transistor that constitutes the equalizers BLE and SAE must have a thickness sufficient to withstand the voltage VCC. On the other hand, since the voltage VBLH is applied to the sense amplifier S/A, the gate oxide film of each MOS transistor that constitutes the sense amplifier S/A only needs to be thick enough to withstand the voltage VBLH.
Conventionally, however, the gate oxide films of all MOS transistors that constitute the sense amplifier S/A, bit line equalizer BLE, and sense amplifier equalizer SAE are formed to be thick enough to withstand the power supply voltage VCC because, for example, the potential difference between the voltages VCC and VBLH is small. Even when the gate oxide film of each MOS transistor that constitutes the sense amplifier S/A is thick, no particular problem is posed because a sufficient driving force can be ensured for the sense amplifier S/A.
Along with the recent reduction in size and power consumption of LSIs, the power supply voltage VCC is becoming low. In a DRAM, a voltage applied to a word line has a close relation to memory cell operation and therefore cannot be decreased. That is, in a DRAM, the power supply voltage VCC serving as a source for generating the voltage to be applied to a word line cannot be decreased. Consequently, in the memory cell array portion of a DRAM, only the value of the voltage VBLH applied to the pair of bit lines BLt and BLc becomes small.
This leads to an increase in potential difference between the voltages VBLH and VCC. If the sense amplifier S/A is constituted by only VCC type MOS transistors with thick gate oxide films, the driving force of the sense amplifier S/A poses a problem.
To solve this problem, MOS transistors each having a thin gate oxide film corresponding to the voltage VBLH are used for the sense amplifier S/A, and MOS transistors each having a thick gate oxide film corresponding to the power supply voltage VCC are used for the equalizers BLE and SAE.
FIG. 5 shows a layout example of the sense amplifier S/A and bit line equalizer BLE, which are connected to a pair of bit lines.
A thick film type Tr area is an area constituted by VCC type MOS transistors, each of which has a gate oxide film that is thick enough to withstand the power supply voltage VCC. A thin film type Tr area is an area constituted by VBLH type MOS transistors each of which has a gate oxide film that is thick enough to withstand the voltage VBLH (<VCC). The gate oxide film of a VBLH type MOS transistor is thinner than that of a VCC type MOS transistor.
The bit line equalizer BLE is formed in the thick film type Tr area. To the contrary, the sense amplifier S/A is formed in the thin film type Tr area to ensure a sufficient driving force even when the voltage VBLH of “H” level is applied to the pair of bit lines BLt and BLc.
As described above, when a plurality of MOS transistors whose gate oxide films have different thicknesses are laid out in the memory cell array portion, an isolation area must be prepared between the MOS transistors having gate oxide films with different thicknesses, i.e., between the thick film type Tr area and the thin film type Tr area, to safely form the MOS transistors. When all the MOS transistors in the memory cell array portion have gate oxide films of the same thickness, the isolation area is unnecessary.
FIG. 6 shows a layout example of the sense amplifier equalizer SAE.
The sense amplifier equalizer SAE is formed in a thick film type Tr area A. At this time, a thin film type Tr area B where the sense amplifier S/A is arranged is adjacent to the thick film type Tr area A where the sense amplifier equalizer SAE is arranged. Hence, an isolation area must be formed between these areas to safely form the plurality of MOS transistors having gate oxide films with different thicknesses.
That is, conventionally, to separate the bit line equalizer BLE from the sense amplifier S/A, an isolation area having a predetermined width in the column direction is necessary. In addition, to separate the sense amplifier equalizer SAE from the sense amplifier S/A, an isolation area having a predetermined width in the row direction is necessary.
As described above, depending on the decrease in “H”-level voltage (VBLH) of the pair of bit lines BLt and BLc, when the sense amplifier S/A is constituted by VBL type MOS transistors, the isolation areas in the memory cell array portion become large, and the layout size of the memory cell array portion increases.
To suppress an increase in layout size of the memory cell array portion, for example, the sense amplifier equalizer SAE is constituted by only VBLH type MOS transistors, as shown in FIG. 7.
In this case, since all transistors that constitute the sense amplifier equalizer SAE can be laid out in the thin film type Tr area B, the isolation area in the row direction as shown in FIG. 6 is unnecessary. In this scheme, however, since the size of each transistor that constitutes the sense amplifier equalizer SAE becomes small, the time required for equalization becomes long.
Hence, a semiconductor memory is demanded, which can prevent any increase in layout size of a memory cell array portion and also suppress any decrease in driving force of a sense amplifier equalizer even when the gate oxide film of each transistor that constitutes a sense amplifier has a thickness different from that of the gate oxide film of each transistor that constitutes a bit line equalizer.